I am trying to design the UART protocol in systemverilog. So the reciever only get the value after the particular ns delay;
First i will use the #13043 ns; It will shows on run time error…
So how to achive the nano second delay in my code.
You can’t have a space between the literal and the ns. It should look like:
#13043ns;
In reply to Rajaraman R:
In the verification of your UART, are you using assertions?
I wrote the following paper on this topic:
In many cases, the traditional monitor/scoreboard/checking can be replaced altogether with assertions. The following paper explains the concept using the verification of a UART as an example (Assertions Instead of FSMs/logic for Scoreboarding and Verification | Verification Horizons | Verification Academy ).: Assertions Instead of FSMs/logic for Scoreboarding and Verification | Verification Horizons | Verification Academy
The END NOTES of that paper provides links to the test code and uart tx and rx models.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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