How to start task (it is in sequence ) from testcase.? how to solve uvm_fatal (neither the item's sequencer nor dedicated sequencer has been supplied to start item in wr_seq)

UVM
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1

Am trying to start the sequence from testcase ,that sequence has one task .

class abc extends uvm_sequence #(pkt)
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task write(bit [15:0] addr, bit [15:0] data)
`uvm_do_with(req,{req.m_hwrite == 1;req.m_hburst == SINGLE;req.m_haddr == addr;req.m_hwdata == data;})

endtask
endclass

in testcase:
class base_test extends uvm_test;
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task run_phase(uvm_phase phase);
		abc wr_seq;		// single register write, read
		super.run_phase(phase);
		wr_seq = abc::type_id::create("wr_seq");
		phase.raise_objection(this);
                  wr_seq.write(16'hEA,16'hAABB);
                  wr_seq.start(env.ahb_env.m_st1_ahb_agent.m_st1_sqr);
                phase.drop_objection(this);

endtask
endclass

in agent:
//at connect phase
m_st1_drv.seq_item_port.connect(m_st1_sqr.seq_item_export);

//am getting below uvm_fatal
UVM_FATAL @ 0: reporter@@wr_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in wr_seq

can any one suggest how to solve this issue.?

thanks,

2

In reply to Rao.Bee:

Could you please show the sequencer definition?

3

In reply to chr_sue:

it is look likes:

class ahb_sqr extends uvm_sequencer #(pkt);
	
	`uvm_component_utils(ahb_sqr)
	
	 function new(string name,uvm_component parent);
	         super.new(name,parent);
	 endfunction

endclass:ahb_sqr
4

In reply to Rao.Bee:

OK, thanks. It looks good.
The sequence does not know a write method. Instead it has a body task. In this task you have to implement how the seq_items should be dreated. It might have insight what you have in your write meothod. Please try the following:
(1) Specify your body task in the sequence like this:

  task body();
    `uvm_do_with(req,{req.m_hwrite == 1;req.m_hburst == SINGLE;req.m_haddr == addr;req.m_hwdata == data;})
  endtask

(2) Remove the write task call from the run_phase in the test.

5

In reply to chr_sue:

thanks chr_sue,

(1)i can use this method but in my testcase each time need to write 3 steps …
means wr_seq.addr= ee;
wr_seq.data = aabb;
wr_seq.start(env.ahb_env.m_st1_ahb_agent.m_st1_sqr);

(2) my requirement is like this.from test .
wr_seq.(16’hee,16’haabb).start(env.ahb_env.m_st1_ahb_agent.m_st1_sqr);

with in one line completed means it could be good.

i hope you understood my requirement.

thanks,

6

In reply to Rao.Bee:

Instead of write you can do:

wr_seq.randomize with {addr ==16'hEA; data == 16'hAABB;};

Then start your sequence.

7

In reply to Rao.Bee:

You can add tasks to your sequence which can be called from the test to accomplish what you want to do. The only additional requirement is that you pass a sequencer to your task so that it knows where to run.


class abc extends uvm_sequence #(pkt)
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  task write(bit [15:0] addr, bit [15:0] data, uvm_sequencer sqr);
    req = pkt::type_id::create("pkt");
    start_item(req, -1, sqr);
    req.m_hwrite = 1;
    req.m_hburst = SINGLE;
    req.m_haddr = addr;
    req.m_hwdata == data;
    finish_item(req);
  endtask
endclass

class base_test extends uvm_test;
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.
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.
 
task run_phase(uvm_phase phase);
		abc wr_seq;		// single register write, read
		super.run_phase(phase);
		wr_seq = abc::type_id::create("wr_seq");
		phase.raise_objection(this);
                wr_seq.write(16'hEA,16'hAABB,env.ahb_env.m_st1_ahb_agent.m_st1_sqr);
                phase.drop_objection(this);
 
endtask
endclass
8

In reply to cgales:

Giving an add-on. This si what the UVM Reference Manual is saying:
virtual task body();
This is the user-defined task where the main sequence code resides. This method should not be called directly by the user.

Writing your own task is legal, but it is not recommended.

9

In reply to chr_sue:

The ideal solution would be to implement a register map which does the same thing without requiring the user to add additional tasks to their sequence.