In reply to Rao.Bee:
You can add tasks to your sequence which can be called from the test to accomplish what you want to do. The only additional requirement is that you pass a sequencer to your task so that it knows where to run.
class abc extends uvm_sequence #(pkt)
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task write(bit [15:0] addr, bit [15:0] data, uvm_sequencer sqr);
req = pkt::type_id::create("pkt");
start_item(req, -1, sqr);
req.m_hwrite = 1;
req.m_hburst = SINGLE;
req.m_haddr = addr;
req.m_hwdata == data;
finish_item(req);
endtask
endclass
class base_test extends uvm_test;
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task run_phase(uvm_phase phase);
abc wr_seq; // single register write, read
super.run_phase(phase);
wr_seq = abc::type_id::create("wr_seq");
phase.raise_objection(this);
wr_seq.write(16'hEA,16'hAABB,env.ahb_env.m_st1_ahb_agent.m_st1_sqr);
phase.drop_objection(this);
endtask
endclass