How to print hexadecimal numbers in upper case

SystemVerilog
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1

In system verilog, when we use $display to print hex numbers, they are in lower case. For example, the following statement:

$display("var=%0h", var)

will get “var=af”.
How can I get “var=AF” with $display?

2

Hello!
Try one of these 2 methods (or both) and get back to me as I’ve done this on Python and not in SV.

  1. $display(“var = %0h{:H}”, var);
  2. $display(“var = %0H”, var);

Please inform if both are working or aren’t or if any one is working.

Hope it helps.

3

In reply to Aaron_Cui:

SystemVerilog has a toupper() string method.

module top;
   logic [15:0] val = 16'hcafe;
   string sval;
   initial begin
      sval.hextoa(val);
      $display("val= %s", sval.toupper());
   end
endmodule
1 Like
4

In reply to Shashank Gurijala:

Hi Mr. Gurijala,

Thanks for your reply. Bad news that neither method works.
5

In reply to dave_59:

Hi Mr. Rich,

Thanks for your reply! Seems that this is the only way.
6

In reply to Aaron_Cui:

Sorry :(

7

In reply to dave_59:

Hi Dave!
Thanks for the solution. But is there a function to convert uppercase letters to lowercase?

8

In reply to Shashank Gurijala:

See section 6.16 String data type in the IEEE 1800-2017 SystemVerilog LRM.