How to print hexadecimal numbers in upper case

SystemVerilog
,
2

Hello!
Try one of these 2 methods (or both) and get back to me as I’ve done this on Python and not in SV.

  1. $display(“var = %0h{:H}”, var);
  2. $display(“var = %0H”, var);

Please inform if both are working or aren’t or if any one is working.

Hope it helps.