How to prevent FIFO Overflow Check Assertion from triggering every clock

SystemVerilog
, ,
1

I have following assertion for detecting FIFO overflow condition in a DUT:

property fifo_wr_good;
  disable iff (rst) @ clk wr_en |-> !full;
endproperty

FIFO_OVERFLOW_ERROR:
  assert property (fifo_wr_good) else begin
    `uvm_error("FIFO_MONITOR", "*** FIFO Overflow Detected!")
  end

The above assertion works fine in detecting FIFO overflows. However, I’d like to modify it so that the error is triggered only at the start of each overflow condition detection. In other words, if ‘wr_en’ and ‘full’ are high for multiple clocks, the error should trigger for the first clock and it shouldn’t trigger again until a new overflow condition is detected after ‘wr_en’ or ‘full’ were de-asserted from previous error. I have tried few different ways using $past but none of them have worked…but I am no assertions expert. Can any show me an easier way of doing this?

2

In reply to Earthling:

disable iff (rst)  @clk $rose(wr_en) |-> !full until !wr_en;
3

In reply to dave_59:

Thanks Dave! That works.