How to model an assertion with delay interms of time units?

SystemVerilog
1

Hi,

I have a requirement for writing an assertion for a protocol where after transmitting a signal x, within 3.5ms to 10ms I have to transmit another signal y. Since we can’t use time delays directly in writing assertion property, can you please, tell me how to write assertions for such cases.

Thanks in advance,
D

2

The simplest way is to write an immediate assertion that compares the time delay between x and y against your requirements. As you experienced, concurrent assertions will not work since you don’t have a clock.

module asn_delay;
// I have a requirement for writing an assertion for a protocol where after transmitting a signal x, 
// within 3.5ms to 10ms I have to transmit another signal y. Since we can't use time delays directly 
// in writing assertion property, can you please, tell me how to write assertions for such cases.
	timeunit 1ns; timeprecision 100ps;
	bit x, y; 
	always @(posedge x) begin 
		automatic realtime t_atx; //  
		t_atx= $realtime; 
		wait(y);
		assert(($realtime-t_atx >= 3.5ms) && ($realtime-t_atx <= 10ms)); 
	end

endmodule
// integer_atom_type ::= byte | shortint | int | longint | integer | time
// non_integer_type ::= shortreal | real | realtime

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Hi Ben,
From the above code we can check for the time between x and y but, if ‘y’ didn’t get asserted, it won’t give assertion fail.
How to check whether ‘Y’ is asserted or not between 3.5 to 10ms?

Regards,
D

4

In reply to Dilip Bagadi:

Good point, forgot about that condition. This should address this. BTW, you may want to add action blocks.
For UVM reports in assertions, see Can we detect SVA in DUT under UVM? | Verification Academy

module asn_delay2;
	// I have a requirement for writing an assertion for a protocol where after transmitting a signal x, 
	// within 3.5ms to 10ms I have to transmit another signal y. Since we can't use time delays directly 
	// in writing assertion property, can you please, tell me how to write assertions for such cases.
	timeunit 1ns; timeprecision 100ps;
	bit x, y; 
	always @(posedge x) begin 
		automatic realtime t_atx; //  
		t_atx= $realtime; 
		fork 
		    begin 
		      wait(y);
		      assert(($realtime-t_atx >= 3.5ms) && ($realtime-t_atx < 10ms)); 
		    end
		    begin 
		    	# 10.0ms;
		    	assert(1'b0);
		    end
		join any; 
	end
endmodule
5

In reply to ben@SystemVerilog.us:

Thanks Ben.

Regards,
D

6

Hello,
I have a question. Since I am new to system verilog assertion, can you please tell me how to verify design using real time delay in clock(Formal verification). For example, if the clock period is 5ns, then at posedge the property should be verified from 2.3 to 2.7ns instead of exactly at 2.5ns.Is this possible? If possible can you give me an example of how to verify it

Thanks in advance,
S

7

In reply to swetha K:

formal verification paths, it does not handle that kind of delay granularity.
Ben