Hello,
I have a question. Since I am new to system verilog assertion, can you please tell me how to verify design using real time delay in clock(Formal verification). For example, if the clock period is 5ns, then at posedge the property should be verified from 2.3 to 2.7ns instead of exactly at 2.5ns.Is this possible? If possible can you give me an example of how to verify it
Thanks in advance,
S