In reply to ben@SystemVerilog.us:
Hi Ben,
From the above code we can check for the time between x and y but, if ‘y’ didn’t get asserted, it won’t give assertion fail.
How to check whether ‘Y’ is asserted or not between 3.5 to 10ms?
Regards,
D
In reply to ben@SystemVerilog.us:
Hi Ben,
From the above code we can check for the time between x and y but, if ‘y’ didn’t get asserted, it won’t give assertion fail.
How to check whether ‘Y’ is asserted or not between 3.5 to 10ms?
Regards,
D