How to Get the Address of a varaible in SV?

SystemVerilog
, ,
9 
class base;

endclass

class trb extends base;
  trb this_trb_p;
  trb next_trb_p;
  bit[7:0] data_buffer_pointer[];
  int status;
  int control;

  function execute_trb();
    $display("execute trb");
  endfunction

endclass

class td extends trb;
  td  this_td_p;
  td  next_td_p;

  trb start_trb_p;
  trb end_trb_p;

  function execute_td();
    m_trb;
    m_trb = start_trb_p;

    do begin
      m_trb.execute_trb();
      m_trb = m_trb.next_trb_p;
    while(m_trb != null);  
  endfunction

  function add_trb(trb add_trb);
    if(start_trb_p == null) begin
      start_trb_p = add_trb;
      end_trb_p = add_trb;
    end  
    else begin
      end_trb_p.next_trb_p = add_trb;
      end_trb_p = add_trb;
    end    
  endfunction  

endclass

class transfer_ring extends td;
  transfer_ring this_tr;
  
  trb dequeue_pointer;
  trb enqueue_pointer;

  td start_td_p;
  td end_td_p;

  function execute_tr();
    td m_td;

    m_td = dequeue_pointer;
    do begin
      m_td.execute_td();
      if(m_td == enqueue_pointer)
        break;
      m_td = m_td.next_td_p;
    while(m_td != null)  

  endfunction

  function add_td(td add_td);
    if(start_td_p == null) begin
      start_td_p = add_td;
      end_td_p = add_td;
    end  
    else begin
      end_td_p.next_td_p = add_td;
      end_trb_p = add_td;
    end    

    dequeue_pointer = start_td_p.start_trb_p;
    enqueue_pointer = end_td_p.end_trb_p;
  endfunction  
endclass  

module test;
  base aa[bit[31;0]];
  trb0 = new();
  trb1 = new();
  td = new();
  transfer_ring = new();

  td.add_trb(trb0);
  td.add_trb(trb1);
  transfer_ring.add_td(td);

  aa[32'h0000_0001] = transfer_ring.dequeue_pointer;
  aa[32'h0000_0002] = trandfer_ring.enqueue_pointer;

  //so address 32'h01 and 32'h02 correspond to dequeue and enqueue
  //you can use register model to access the two addresses

endmodule