How to Get the Address of a varaible in SV?

SystemVerilog
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7

In reply to Naven8:

Hi Naven8,

Thanks for the quick reply. I am currently working on HOST CONTROLLER INTERFACE for USB-3.0. In that Project I have a requirement like this:
I have to construct TRANSFER RINGS. Basically a Ring is a circular queue data structure. Ring Size is not fixed. So for that I am using variable like this:
bit [31:0] RING [$];
And the problem is, I should write the base address/ starting address of the RING variable in another Register DEQUEUE POINTER field. The Register was implemented using UVM Register Model. How can we address this problem?

Thanks & Regards
Naveen