Hi all,
I have a verilog module which consists of a tasks.
Is it possible to call these tasks from the sequence/Test of my verification Environment.
If possible, How can this be done?
Regards,
Santosh Kumar
In reply to santosh_kumar_vangala:
its possible to call task of verilog module in verification environment written in system verilog or UVM.
module top
task get_data();
endtask
endmodule
Then the above task can called from driver or test case in following fashion.
top.get_data();
SystemVerilog won’t allow hierarchical references to modules from within packages, which is the recommended method for implementing your UVM environment. The reason for this is to enforce portability of your packages and make re-use easier.
You can either copy your tasks into your driver, which should be easy if the functions are independent and not dependent on any module internals. If the module contains only functions, you can convert it to an interface and use the uvm_config_db to pass the virtual interface handle into your testbench and access the functions via the interface handle.
Use the abstract/concrete class mechanism
http://www.doulos.com/downloads/events/DVCon_08_abstractBFM_final.pdf
In reply to cgales:
Hi,
Thanks for the response.
I don’t have access to the design. Just the name of the task and arguments are know to us.
Presently I’m following a method to overcome this problem:
There are two interface signals, and whenever any of the two signals is changed, this task of the design must be called.
My testbench_top consists of the instantiation of the design_top.
In testbench_top module, we have written an always block, whose sensitivity list consists of these two interface signals. From this always block the task in the design is called.
Is there any other method, so that I can call this task of design?
My Idea is to move always block code from testbench_top to any other place in verification Environment. Is this possible?
- Santosh