How to call a verilog task in RTL from the test

UVM
,
4

Use the abstract/concrete class mechanism

http://www.doulos.com/downloads/events/DVCon_08_abstractBFM_final.pdf

https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection

http://events.dvcon.org/2015/proceedings/papers/04P_19.pdf