In reply to cgales:
Hi,
Thanks for the response.
I don’t have access to the design. Just the name of the task and arguments are know to us.
Presently I’m following a method to overcome this problem:
There are two interface signals, and whenever any of the two signals is changed, this task of the design must be called.
My testbench_top consists of the instantiation of the design_top.
In testbench_top module, we have written an always block, whose sensitivity list consists of these two interface signals. From this always block the task in the design is called.
Is there any other method, so that I can call this task of design?
My Idea is to move always block code from testbench_top to any other place in verification Environment. Is this possible?
- Santosh