How to bypass assertions using $assertoff/$asserton

SystemVerilog
1

Hi,

I have requirement of disabling assertions for some time after reset and enabling it again. I know $asserton and $assertoff can be used for this purpose but not aware of how and where to use them.

Presently, Assertions starts firing as soon as DUT comes out of Reset. But still, some signals goes to X for certain duration after RESET. How to use $asserton and $assertoff to bypass assertions for this particular duration after RESET?

Kindly, help me to find the soulution.

Thank you.

2

A quick and easy fix is to add an initial block in your top level testbench that can handle the assertion control:


initial begin
  $assertoff;
  #100ms;
  $asserton;
end

You can create something more complex if you need to wait for specific signals or conditions.

3

In reply to cgales:

Hi cgales,

This will disable and enable all the assertions. Please, let me know, how can we disable and enable them for only some particular assertions instead of all of them.

4

In reply to bpdacha:

The SystemVerilog LRM contains the complete details about using $asserton and $assertoff. It is way too complex to explain here, so I recommend reading it if you want some finer control over which assertions you want to control.

5

Hi,

If your requirement is to disable perticular assertion for any specific testcase then you can use “disable iff” feature of assertion

Ways to use it

  1. disable on perticular signal (either DUT/ generate as per your requirment)
  2. disable on bit which you can take it from run time option($value$plusargs/$test$plusargs)

Hope it will help you.

Regards,
Vinay Jain

6

In reply to Vinay Jain:

Thank you Gales and Vinay for your valuable inputs.