How to bypass assertions using $assertoff/$asserton

SystemVerilog
5

Hi,

If your requirement is to disable perticular assertion for any specific testcase then you can use “disable iff” feature of assertion

Ways to use it

  1. disable on perticular signal (either DUT/ generate as per your requirment)
  2. disable on bit which you can take it from run time option($value$plusargs/$test$plusargs)

Hope it will help you.

Regards,
Vinay Jain