Help in finding better way to restructure the code

SystemVerilog
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2

In reply to rahulkumarbudhwani:
See if this model provides some answers for you.
http://systemverilog.us/vf/sem.sv

1590×875 134 KB

1590×875 134 KB


module top;
    timeunit 1ns;  timeprecision 100ps;    
    `include "uvm_macros.svh"
    import uvm_pkg::*;
    bit clk, cond;
    semaphore smTx;
    event e1, e_other; 
    initial  smTx=new(1);
    default clocking @(posedge clk);
    endclocking
    initial forever #10 clk = !clk;


   /* I have a logic where a semaphore waits for key only if a particular condition is not set 
    and once I gather the key, I release after clocking block statement one cycle later. 
    However, if a condition is set, therefore, it checks in next cycle for the key. 
    I think my implementation in the code is too clumsy. 
    The issue in this logic is that when we check for key every cycle, 
    we might miss the key as the thread which releases the lock runs later 
    and we get the lock in next cycle. 
    Therefore, I need help re-structuring the code and the logic is shown below. */
    task automatic t1();	
        // If the specified number of keys is available, the method returns and execution continues. 
        // If the specified number of keys is not available, the process blocks until the keys become available.	 
        smTx.get(1); 
        $display("%t t1 got key", $time); 
        -> e1; 
           // drive some signals 
        @(posedge clk) smTx.put(1);
        $display("%t t1 PUT key", $time); 
	endtask

    task automatic t_other();
        smTx.get(1); 
        $display("%t t_other got key", $time); 
        -> e_other;
        #20;
           // drive some signals 
        @(posedge clk) smTx.put(1);
        $display("%t t1_other PUT key", $time); 
        
    endtask

    always @(posedge cond) begin 
       fork
           t1(); 
           t_other(); 
       join_any 
    end 
   
  
    initial begin
       bit[1:0] d; // delay
       bit c; // condition 
       realtime r;
      repeat (200) begin
        @(posedge clk);
        if (!randomize(c, d) with {
          c dist {1'b1 := 1, 1'b0 := 4};
        })
          `uvm_error("MYERR", "This is a randomize error");
         r= d*1ns; 
         #r; 
        cond <= c;
      end
      $finish;
    end
  endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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