Generate clk only when desired

UVM
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1

Hi,

I have a question regarding generating and holding the clock as desired.
I know its quite wage let me stage it in detail below.

my sequence_item generates random values constraint in certain range for few variables.
In my driver sum of all, the above-generated values give me numClks-> this the number for which I want to generate clocks while driving my enable signal low.

Now, here is my question, there is another signal call hold which when generated my clocks should keep running but numClks should just be frozen till the hold is de-asserted.

Explaining the question using an example.
Assume numClks = 10.
driver asserts enable and start generating clk for 10 cycles, but sees the hold signal after 5 clocks generated for 100 ns.
thus, the driver should keep driving the clk at the interface for 100 ns but should not account for decrementing of numClks post 100ns it should start decrementing numClks and generate 5 more remaining clks.

I am trying to accomplish the above using event and trigger, but not able to achieve the desired result in the waveform.
Any idea or approach will greatly be appreciated.

Please let me know, I can share my pseudo code if desired.

Thanks & Regards,
Piyush

2

In reply to PIYUSH PANWAR:

I am sorry to say, your question simply indicates a lack of basic digital fundamentals.
Here is my suggestion:

  1. don’t jump into UVM yet
  2. take basic digital blocks and code them using RTL
  3. simulate your code
  4. once you are done with 2 & 3, come back to UVM and code your driver

You will realize that without digital fundamentals, you will hardly be able to code basic driver and monitor, much less debug RTL designs.

3

In reply to verif_learner:

Thanks for your suggestion. I really appreciate it. And value it really in high regards.
But, I have always work on the design with free-running clock and the current project requires something different. Thus, was my question.

But, thanks again for your very valuable suggestion.
I am still looking for some solution for the above-expressed query.

Thanks & Regards,

4

In reply to PIYUSH PANWAR:

Hi All,
I am posting the solution for someone who is looking achieve the same thing what I was trying.

Hope it helps. (you will need to do this or something similar if trying to implement SPI interface verification component.)

fork
  begin
    while (device_enable && numClks !=0)
    begin
      gen_clk
      if (!device_on_hold)
        begin  
          numClks--;
          drive_valid_data_on_data_bus();
        end
      if (device_on_hold)
        begin
          drive_random_on_data_bus();
        end 
    end 
  end
join

task gen_clk();
  #5 clk <= 1;
  #5 clk <= 0;
endtask

Thanks for your help and valuable pointers.

Thanks & Regards,
Piyush

5

In reply to PIYUSH PANWAR:

It looks like you are doing very simple things quite complicated. You can generate your clock all the time. Dependend on the requirements you have you can make this clock available to a certain component using a clock enable signal.