Generate clk only when desired

UVM
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In reply to PIYUSH PANWAR:

I am sorry to say, your question simply indicates a lack of basic digital fundamentals.
Here is my suggestion:

  1. don’t jump into UVM yet
  2. take basic digital blocks and code them using RTL
  3. simulate your code
  4. once you are done with 2 & 3, come back to UVM and code your driver

You will realize that without digital fundamentals, you will hardly be able to code basic driver and monitor, much less debug RTL designs.