Generate a clock of of exact 200MHz

SystemVerilog
,
1 
`timescale 1ns/1ns

module test;
bit clk=0; 
realtime delay=2.5;

initial
begin 
#delay clk=~clk;
end

initial
begin 
#2ms;
$finish;
end

endmodule

Half clock period is taking 3ms ?
How to resolve this

2

Your time precision as defined by the `timescale directive is 1ns, so all delays in the modules that follow that directive will be rounded to the nearest ns. So you need to use a time precision of 100ps or less.

Also, since you are using SystemVerilog, we recommend using the timeunit/timeprecision constructs inside the module instead of `timescale outside of a module. And always use time literals

module test;
timeunit 1ns;
timeprecision 100ps;
bit clk=0; 
realtime delay=2.5ns;
 
always
  begin 
    #delay clk=~clk;
  end
 
initial
  begin 
   #2ms;
   $finish;
  end
endmodule
3

In reply to dave_59:

Dave,
You mean the following, per your text comments:


timeunit 1ns;
timeprecision 100ps;
4

In reply to ben@SystemVerilog.us:

Thanks. Corrected.

5

In reply to dave_59:

@Dave why using timeunit/timeprecision is recommended instead of using `timescale outside module? I mean what difference does it make to that module?

6

In reply to Abhyudha:

The `timescale compiler directive specifies the default time unit and precision for all design elements that follow this directive and that do not have timeunit and timeprecision constructs specified within the design element.

Defining the timeunit and timeprecision constructs within the design element removes the file order dependency problems with compiler directives. There shall be at most one time unit and one time precision for any module, program, package, or interface definition or in any compilation-unit scope. This shall define a time scope.

You can also checkout the precedence of timeunit, timeprecision, and `timescale in LRM.

7

In reply to Sushrut Veerapur:

Hi Dave,

I coded a simple example.
But actually in my Soc Verification design , top level is using the timescale of 1ns/1ns.
I dont have permisssion to change the timescale.
One IP whcih needs to integrate uses 200MHz clock.

Now, I dont have permission to change timescale and i need generate 200MHz
HOW?

8

In reply to naaj_ila:

You have a few options

  1. Ask for permission to change the precision to 100ps of the top module.
  2. Change the duty cycle of the clock to 60/40 (2ns high/3ns low).
  3. Put the clock generator in a module with one output port, and make the precision of that module 100ps. Then instantiate that module in your top module.
9

In reply to dave_59:

Thanks a lot Dave ,

I got it