Your time precision as defined by the `timescale directive is 1ns, so all delays in the modules that follow that directive will be rounded to the nearest ns. So you need to use a time precision of 100ps or less.
Also, since you are using SystemVerilog, we recommend using the timeunit/timeprecision constructs inside the module instead of `timescale outside of a module. And always use time literals
module test;
timeunit 1ns;
timeprecision 100ps;
bit clk=0;
realtime delay=2.5ns;
always
begin
#delay clk=~clk;
end
initial
begin
#2ms;
$finish;
end
endmodule