Force a signal

SystemVerilog
, ,
1

program test ;

bit [0:11] a;

initial begin
for (int i=0 ; i <12 ;i++) begin
force a[i] = ~a[i];
$display(“element %h is = %h”, i, a[i]);
end
end

endprogram

I tried to run this program but I am getting the below errors .
→ illegal operand for constant expression .

2

In reply to withankitgarg:

Use big case

case(bit_sel)
0: force TOP.DUT…BUS_TO_BE_FORCED[0] = …
…etc

3

In reply to rahulkumarkhokher@gmail.com:

2 comments:

  1. Your “i” is an automatic variable as it is declared internally by the for. Movie it outside for it to work well.
  2. You don’t need a force, just use assignment.
program test ;

bit [0:11] a; 
int i;
  
initial begin 
for (i=0 ; i <12 ;i++) begin
 a[i] = ~a[i];
$display("element %h is = %h", i, a[i]);
end 
end

endprogram

Srini
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