Factory override of uvm_sequence(uvm_object) in one of the interfaces (agents)

UVM
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Hi VA,

A DUT has similar 16 interfaces, meaning same uvm_sequence_item is wiggled on input pins.
Is it possible to override and change the behavior of only one of the items?
For example: I would like to set different delays for IF#0 than for the other IFs.
Tried using next function: set_type_override
But it override all the sequences.
Since object does not have a parent, how can this be achieved?

Thanks,
Michael

2

In reply to Michael54:

Do you want to Override Request Item ( of type extended from uvm_sequence_item )
OR user_sequence ( of type extended from uvm_sequence ) ?

If it’s user_sequence , are these created from test Or as Sub-Sequence ?

It’s best if you could share a small code snippet along with the TB Topology .

Also using set_inst_override would be the preferred way .

3

In reply to ABD_91:

Please not set_inst_override is restricted to uvm_components and the sequence does not have a position in the topology of the testbench. You cpuld try to relate the sequence to the sequencer path.
Why not reate a different test with the extended and the original sequences. Even using the override requires a new test.

4

In reply to chr_sue:

I believe that’s incorrect .
Here’s a LINK

I don’t recollect reading anywhere ::
set_inst_override is restricted to uvm_components

Could you please elaborate on it .

I personally have practiced codes ,
Overriding Sequences and Sequence_Items using instance override .

5

In reply to ABD_91:

I’m refering to
A convenience function for uvm_factory::set_inst_override_by_name, this method registers a factory override for components created at this level of hierarchy or below.
In the UVM Reference Manual and the fact a sequence itself does not have position in the topology of the testbench.
But I said also you might be able to refer to the sequencer the sequence will be executed.

6

In reply to ABD_91:

It does not really matter if it is uvm_sequence or uvm_sequence_item, as are both inherited from the uvm_object.
Look at the next link of inheritance:
https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1c/html/files2/sequences-txt.html

I specifically asking how to override a uvm_object which does not have a position in a testbench as it does not has a parent.

And the function set_inst_override is present only under the uvm_component source code.
Open the UVM uvm_object file and look after set_inst_override, you won’t find it.

7

In reply to chr_sue:

In reply to ABD_91:
Please not set_inst_override is restricted to uvm_components and the sequence does not have a position in the topology of the testbench. You cpuld try to relate the sequence to the sequencer path.
Why not reate a different test with the extended and the original sequences. Even using the override requires a new test.

I would like to create stimuli in the same test, in order to define different delays for sequences passing on IF#0, and different delays on other IFs for stress purposes.
Which factory functions are advised to achieve override of uvm_objects(and their children)? Since it does not have a test-bench topology path…

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In reply to Michael54:

Please look here:

But I did not check if this works.

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In reply to chr_sue:

Thanks Christoph,
I will try to go over the post and the paper Tudor added in the post.
Will try update the post here with the findings.

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In reply to Michael54:

class uvm_object_registry also defines function set_inst_override .

Assuming that you use macro `uvm_object_utils for the Sequence and Sequence_item
you would be able to use set_inst_override for them .


 base_type  ::  type_id :: set_inst_override ( ext_type ::  get_type() , "<STRING_PATH>"  ) ;

Objects like User_sequences can be created and started from Test .
During create the parent argument can be used as ’ this ’
( referring to the test component ) and
overridden from Test’s build_phase() using set_inst_override with string_path as

“uvm_test_top.seq_instance_name”