In reply to chr_sue:
In reply to ABD_91:
Please not set_inst_override is restricted to uvm_components and the sequence does not have a position in the topology of the testbench. You cpuld try to relate the sequence to the sequencer path.
Why not reate a different test with the extended and the original sequences. Even using the override requires a new test.
I would like to create stimuli in the same test, in order to define different delays for sequences passing on IF#0, and different delays on other IFs for stress purposes.
Which factory functions are advised to achieve override of uvm_objects(and their children)? Since it does not have a test-bench topology path…