Hi all, I am trying to access signals through modport in my sub-module(DUT) and for that, I am using (interface.modport) in a module and in dut_wrapper which is a wrapper I am passing (interface_instance) in wrapper module. The code is passing but I have doubt whether dut(sub-module ) is using interface signal or modport signal.
Here My intention is to use modport for signal driving.
Please clear my doubt.
Thanks in advance
The used code is shared below -:
module Testbench;
parameter tb_data_size=16;
parameter tb_array_depth=10;
bit clk;
int clk_count;
// clock generation
assign dut_wrapper.clk = clk;
always #1 clk = ~ clk;
// Simulation temination based on clock count
always @(posedge clk) begin clk_count++; end
always @(negedge clk) begin if(clk_count == 20) $finish; end
// instatiation of different rtl
//intf#(tb_data_size) d_if(clk); // interface instance
// stimulation genration and drive
reg [tb_data_size-1:0]inp1[tb_array_depth];
// reg [tb_data_size-1:0]inp2;
wire[tb_data_size:0]out1[tb_array_depth];
assign dut_wrapper.d_if.inp1 = inp1;
//assign dut_wrapper.d_if.inp2 = inp2;
assign out1 = dut_wrapper.d_if.out1 ;
initial
begin
// initialization
clk_count = 0;
foreach (inp1[i]) inp1[i] = 0;
// inp2 = 0;
#2;
// stimulas
//repeat(10)
for(int i=0; i<= 10; i++)
begin
#2
//inp1 = $urandom_range(15,40);
foreach (inp1[i])
inp1[i] = $urandom;
// inp2 = $urandom_range(50,60);
end
end
reg [tb_data_size:0]r_out1[tb_array_depth];
int add_er;
always @(posedge clk)
begin
foreach (inp1[i])
r_out1[i] = inp1[i] ;
end
always @(negedge clk)
begin
foreach (out1[i])
if(r_out1[i] != out1[i]) add_er ++;
end
// display statement
always @(posedge dut_wrapper.d_if.clk)
begin
foreach (inp1[i])
$display(":*TB:input1=%0d output1=%0d",inp1[i],out1[i]);
end
//final
final
begin
if(add_er != 0)
$display("\n Test Failed:\n dut checking max arry size not working correct");
else
$display("\n Test Passed:\n dut checking max array size working correct");
end
endmodule
interface intf#(data_size,array_depth)(input bit clk);
logic [data_size-1:0]inp1[array_depth];
// logic [data_size-1:0]inp2[array_depth];
logic [data_size:0]out1[array_depth];
modport mp(input clk,input inp1,output out1);
endinterface
module dut_wrapper;
parameter dut_data_size=16;
parameter dut_array_depth=10;
reg clk;
reg [dut_data_size-1:0]inp1[dut_array_depth];
wire[dut_data_size:0]out1[dut_array_depth];
// rtl and other instantiation
intf#(dut_data_size,dut_array_depth) d_if(clk);
dut#(dut_data_size,dut_array_depth) dut1(d_if);
//initial foreach (inp1[i]) $monitor($time,,":DUT_wraper: input1=%0d output=%0d",inp1[i],out1[i]);
always @(posedge clk) foreach (inp1[i]) $display($time,,":DUT_wraper: input1=%0d output=%0d",d_if.inp1[i],d_if.out1[i]);
endmodule
module dut#(data_size,array_depth)(intf.mp d1);
//module dut#(data_size,array_depth)(clk,inp1,out1);
//parameter size = 8
//input clk;
//input [data_size-1:0] inp1[array_depth];
//output [data_size:0]out1[array_depth];
reg [data_size:0] r_out1[array_depth];
assign d1.out1 = r_out1;
always @(posedge d1.clk)
begin
foreach (d1.inp1[i])
r_out1[i] = d1.inp1[i];
foreach (d1.inp1[i])
$display($time,,":DUT:input1=%0d output=%0d",d1.inp1[i],d1.out1[i]);
end
endmodule