Error with SV Interface wrapper for Verilog DUT

SystemVerilog
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3

In reply to sbellock:

Thanks for your response and insight into this.

Even if I do like shown below, it throws error saying “Unconnected interface port”

//---------Wrapper------
module add_wrap(aif);

adif.dut aif;

add i_add( .a(aif.a), .b(aif.b), .sum(aif.sum), .cout(aif.cout));
endmodule

Thank you once again for your response.