ERROR: Variable(SV: logic/bit) is assigned by multiple continuous statements

SystemVerilog
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1

Hello everyone,

I was writing some code and had this error while building the code:


assign MySignal = input1 ? 1'b1 : 1'b0;
assign MySignal = input2 ? 1'b1 : 1'b0;

(continuous assignment)

and got the error : Variable(SV: logic/bit) is assigned by multiple continuous statements

I did many searches, and found that multiple assignments for the same variable are not possibles, unless the conditional operator ? is used, as the one in the code above, which means that my code is supposed to work, but I don’t know why it doesn’t.

2

In reply to Yasmine4:

You have two assign statements to MySignal. Which one would you expect to take priority? This is why an error is generated.

Perhaps you want:


assign MySignal = (input1 | input2) ? 1'b1 : 1'b0;
3

In reply to cgales:

Also see What's the deal with those wire’s and reg’s in Verilog - Verification Horizons

4

In reply to dave_59:

In reply to cgales:
Also see What's the deal with those wire’s and reg’s in Verilog - Verification Horizons

Usage of ‘wire’ instead of variable when there are multiple assignments concerning the same signal,
Thank you.
it no longer displays that error. works fine I suppose.