Error-[SE] Syntax error Following verilog source has syntax error : "../test/router_test_pkg.sv", 33: token is 'endpackage' SystemVerilog keyword 'endpackage' is not expected to be used in this context

UVM
1

Error-[SE] Syntax error
Following verilog source has syntax error :
“…/test/router_test_pkg.sv”, 33: token is ‘endpackage’

SystemVerilog keyword ‘endpackage’ is not expected to be used in this
context.

package router_test_pkg;


	import uvm_pkg::*;

	`include "uvm_macros.svh"
`include "write_xtns.sv"
`include "write_config.sv"
`include "read_config.sv"
`include "env_config.sv"
`include "write_driver.sv"
`include "write_monitor.sv"
`include "write_sequencer.sv"
`include "write_agent.sv"
`include "write_agent_top.sv"
`include "write_sequence.sv"

`include "read_xtns.sv"
`include "read_monitor.sv"
`include "read_sequencer.sv"
`include "read_driver.sv"
`include "read_sequence.sv"
`include "read_agent.sv"
`include "read_agent_top.sv"
`include "virtual_sequencer.sv"
`include "virtual_sequence.sv"
`include "scoreboard.sv"

`include "env.sv"


`include "test.sv"
endpackage
2

In reply to jayath2000:

Many syntax errors are problems with the line before the reported location. I suspect you are missing an endclass in test.sv.

3

In reply to dave_59:

[quote]In reply to jayath2000:

Many syntax errors are problems with the line before the reported location. I suspect you are missing an endclass in test.sv.

no end the class in test.sv

4

In reply to jayath2000:

How do you compile your code?
You have this package and you need also a toplevel module.

5

In reply to chr_sue:

its a project of router 1*3 i had all the top test env agent
i dont know where i am getting error

6

In reply to jayath2000:

Then you should start and comment-out all includes from line 2 until the end.
Then you can debug your code. You are missing somewhere endclass or any other end.