Error-[SE] Syntax error Following verilog source has syntax error : "../test/router_test_pkg.sv", 33: token is 'endpackage' SystemVerilog keyword 'endpackage' is not expected to be used in this context

UVM
2

In reply to jayath2000:

Many syntax errors are problems with the line before the reported location. I suspect you are missing an endclass in test.sv.