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I have an assertion in a bus arbiter, I want to check that the input request will be present at the output in less than 18 cycles.
I am using something like this, when there is a request, I store the request in a register. The assertion checks that before 18 cycles I will see an output request with the same address.
This assertion never pass or fail. I wanted to know if another style of coding this assertion could be better, so it could pass.
In reply to jcastillo:
The issue with your approach is that you are not necessarily capturing the value of reg_dr0 at the attempt phase as the if(reg_dr0.wr) may occur again at a later cycle. You really need to understand the concept of independent threads. This is how you fix this:
I strongly suggest that you carefully read my paper Understanding the SVA Engine Verification Horizons - July 2020 | Verification Academy
In it I used three different types of SVA properties are used to
emphasize different important concepts of SVA:
Antecedent/consequent: This model demonstrates the concepts of spawned threads,
leading clocking event, attempts.
Range delays in the consequent: This model demonstrates the testing of each element of the
range until success is reached and the lack of need to limit the ranges to a matched (i.e., valid) consequent.
Range delays in the antecedent: This model demonstrates the testing of each element of the
range and the need for a first_match operator or other technique to limit the ranges to a matched antecedent.