In reply to jms8:
I was in the SVA 1800 committee, but not in the main sv language committee.
It is odd that you can put a value on a wire thru a procedural block (task) using a clocking block. 1800 says “Writing to such an inout clockvar shall be equivalent to writing to the corresponding output clockvar”. Looks to me that this is bypass way to remove the restriction that a wire cannot be driven by a procedural block.
Would like to hear about this topic from someone in the language committee who can clarify how this came about.
Ben systemverilog.us