Driving a wire from a task in an interface

SystemVerilog
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3

In reply to jms8:

They’re both illegal.

P1800-2012, section 25.9:

In order for a net to be driven via a virtual interface, the interface itself must provide a procedural means to do so. This can be accomplished either via a clocking block or by including a driver that is updated by a continuous assignment from a variable within the interface.

Your example driver code doesn’t use your clocking block, but are you in fact actually using it? That makes all the difference.

class big_driver extends uvm_driver #(big_item);

    protected virtual big_ifc m_big_vif;

    // Bunch of driver stuff

    task set_all_x_high();
        m_big_vif.x <= 6'b111_111;
    endtask

endclass : big_driver

[/quote]

If your simulator is allowing the above example code, looks to me like it violates the standard.