Difference between SystemVerilog 3.1a LRM by Accellera and IEEE Standard for SystemVerilog

SystemVerilog
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I realized quite recently that there exists two distinct documents that could serve as a “reference” to learn the SV language.

Looking at both, I find the 3.1a LRM to be much more comprehensive with the right amount of detail. The IEEE Standard seems to be quite verbose, although, both of these documents have very similar content. So what is the difference between the two?

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In reply to vk7715:

The difference is the Accellera 3.1a version nearly 20 years old, has lots of mistakes, obsolete, and only contains the enhancements SystemVerilog made over the Verilog 1364-1995 standard. So do not use it.

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3.1a is a historical document that should be in a museum to be observed with curiosity. You shouldn’t implement a simulator from it, or write SystemVerilog code against it.

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In reply to dave_59:

Thank you Dave. I shall stick to the IEEE standard.

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In reply to dave_59:

In reply to vk7715:
The difference is the Accellera 3.1a version nearly 20 years old, has lots of mistakes, obsolete, and only contains the enhancements SystemVerilog made over the Verilog 1364-1995 standard. So do not use it.

Hi Dave, sorry for the delayed follow up question. But in your other posts, when you say “LRM”, are you actually in fact referring to the IEEE standard for SystemVerilog?

Up until now, I always thought the LRM was 3.1a document by Accellera

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In reply to vk7715:

IEEE 1800-2017 SystemVerilog LRM

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In reply to dave_59:

Thank you Dave

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In reply to dave_59:

Language Reference Manual (LRM): A document describing the syntax, semantics, and usage of a programming language. SystemVerilog LRM refers to this standard.