Difference between SystemVerilog 3.1a LRM by Accellera and IEEE Standard for SystemVerilog

SystemVerilog
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In reply to dave_59:

In reply to vk7715:
The difference is the Accellera 3.1a version nearly 20 years old, has lots of mistakes, obsolete, and only contains the enhancements SystemVerilog made over the Verilog 1364-1995 standard. So do not use it.

Hi Dave, sorry for the delayed follow up question. But in your other posts, when you say “LRM”, are you actually in fact referring to the IEEE standard for SystemVerilog?

Up until now, I always thought the LRM was 3.1a document by Accellera