Difference between onehot() and onehot0()

SystemVerilog
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Hi,

I have read the difference between onehot and onehot0 on several blogs but I am not sure how they differ because onehot() is only 1 bit out of n bits should be one at any given time which means the rest of the bits are 0. And onehot0() says atmost 1 bit should be high with all remaining values 0.

Please correct me if my understanding is wrong. I’m unable to spot the difference.

Any help is appreciated.

Thanks in advance.

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In reply to sk9:

Section 20.9 Bit vector system functions in the IEEE 1800-2017 SystemVerilog LRM answers this:

$onehot ( expression ) returns true (1’b1) if $countbits(expression,'1)**==**1, otherwise it
returns false (1’b0).

$onehot0 ( expression ) returns true (1’b1) if $countbits(expression,'1)**<=**1, otherwise it
returns false (1’b0).

1 Like
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In reply to dave_59:

In reply to sk9:
Section 20.9 Bit vector system functions in the IEEE 1800-2017 SystemVerilog LRM answers this:

$onehot ( expression ) returns true (1’b1) if $countbits(expression,'1)**==**1, otherwise it
returns false (1’b0).

$onehot0 ( expression ) returns true (1’b1) if $countbits(expression,'1)**<=**1, otherwise it
returns false (1’b0).

Hi Dave,

$onehot0 is not clear to me. Could you please check this example?

Example : If we have [1:0] state variable,

$onehot will return true for states 2’b01 and 2’b10.
$onehot0 will return true for states 2’b00, 2’b01 and 2’b10.

Is my understanding correct?

Thanks.

1 Like
4

In reply to UVM_learner6:

It seems that it is clear to you.

5

In reply to dave_59:

In reply to UVM_learner6:
It seems that it is clear to you.

Thank you, Dave.