In reply to sk9:
Section 20.9 Bit vector system functions in the IEEE 1800-2017 SystemVerilog LRM answers this:
$onehot ( expression ) returns true (1’b1) if $countbits(expression,'1)**==**1, otherwise it
returns false (1’b0).
$onehot0 ( expression ) returns true (1’b1) if $countbits(expression,'1)**<=**1, otherwise it
returns false (1’b0).