Difference between nettype and "wire logic"

SystemVerilog
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1

What is the difference between nettype and “wire logic”. Can you please explain with example?

I Know the below details.

For “wire logic” there is an inbuilt resolution function and for “nettype”we can have our own resolution function, we can drive whatever the data that we want to drive (4-state data, 2-state data,real value data),i.e., we can define the type of driving data in case of “nettype”.

Can you please explain with some examples on advantages of nettype over “wire logic”?

2

nettype was added to SystemVerilog primarily for Analog modeling; either entirely within SystemVerilog, or interfacing with another analog modeling language. And example would be using the sum of a set of real number drivers to cross a threshold value that would be converted to a digital 0 or 1.

Although having the ability to create any arbitrary resolution function might be ideal, in practice, this functionality needs to be limited to a set of standard resolution functions for interoperability and performance. That standard has yet to be defined.

3

In reply to dave_59:

Hi Dave,

Thanks for your answer. can you please give one simple example for nettype with resolution function.

Thanks in advance.

4

In reply to sivaj:

There is an example at the end of section 6.6.7 User-defined nettypes that sums the value from multiple real drivers

5

In reply to dave_59:

Hi Dave,

Thanks for your answers i write one simple program as shown below but i was unable to use the resolution function. Could you please give me the code on how can i use the resolution function in this case.

typedef struct {
real field1;
real field2;

} T;

function automatic T Tsum
(input T driver);
//Tsum.filed1 = 0.0;
foreach(driver[i])
Tsum.field1 += driver[i].field1;
endfunction

// a nettype whoose data type is T and resolution function is Tsum
nettype T wTsum with Tsum;
module foo (foo_p);
output wTsum foo_p;
wTsum q;

assign q=foo_p;
assign foo_p = T’{14.5,2.5};

endmodule