nettype was added to SystemVerilog primarily for Analog modeling; either entirely within SystemVerilog, or interfacing with another analog modeling language. And example would be using the sum of a set of real number drivers to cross a threshold value that would be converted to a digital 0 or 1.
Although having the ability to create any arbitrary resolution function might be ideal, in practice, this functionality needs to be limited to a set of standard resolution functions for interoperability and performance. That standard has yet to be defined.