Difference between attributes and system verilog assertions

SystemVerilog
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1

Hi,
What is the difference between attributes and system verilog assertions? Where can use them? Is there any differences between them.

2

In reply to perumallatarun:

You must be using the wrong words as these are completely difference concepts.

Attributes are markers in the source text to be used by tools as they wish. Their intent is to be used instead of comments, which are removed by pre-processors.

Assertions are temporal checkers that execute as part of a simulation.

3

In reply to perumallatarun:

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Hi Dave,
Can you please elobarate it. I did not get the advantage of having them.