Define integer range in Systemverilog

SystemVerilog
1

In VHDL I can declare signals as below:
signal cntr : integer range 0 to 31;
So the values of cntr can be any integer value from 0 to 31.

How can I make the same definition and/or workaround in systemverilog?

2

In reply to moustafaali:

bit [4:0] cntr;
3

In reply to Jeff Chen:
and what about ?
signal cntr : integer range 0 to 20;

4

In reply to moustafaali:

integer cntr;
assert #0 (cntr inside ([0:20]);
5

In reply to dave_59:

if i make increment like “cntr = cntr +1 ;”
the assert syntax give error if cntr exceed the max value.
in the vhdl range syntax the cntr will return to 0 after reach the max value(overflow).

anyway it seems that there is no definition for this operation so i will make it using if statement checking the max value.

thanks for your time.