Create Class names with Macro

UVM
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1

I wanted to create class names using macro. The class are of type uvm_reg and there are 31 such classes named as :
PMT_1, PMT_2 and so on until PMT_31.
The object of teh class is already created in other file where the class is deifned.

I want to just call the class with its read function
For eg:
m_reg. PMT_1. read();

Doing it for all 31 registers is a hectic work.

Trying to use Macro:

`define createPMT(i) PMT_``i

ANd within for loop calling out this macro:

for(int i=0;i<32;i++) begin
m_reg.`createPMT(i).read()

This does not work. Can you please provide a solution to it because I have many classes similar to this.
Could this be done using generate and if yes. HOW?

2

In reply to mayubh:

You cannot use macros with for loops if you want to pass the loop index as an argument to the for loop. This is because macros get expanded in a pre-processing step before any SystemVerilog code gets parsed.

You need to explain what code you want created without using any macros. What can you not use a regular array of class variables.