Cover property issue

SystemVerilog
,
1

region0_nonsec_check_mpu16 : assert property(@(posedge clk)
disable iff(AHB_LITE.ahb_htrans===2'b0 || disable_assertion==1 ) (haddr_in_r0 ) |-> ((mpu_region_s_r0 | set_ext_flag) !=AHB_LITE.ahb_hnonsec)) else $fatal("\nERROR: set for MPU16 HIT_Region0 ");

later i have written

cover_region0_nonsec_check_MPU16 : cover property (region0_nonsec_check_mpu16);

i have written one assertion and later i m trying to cover the same but getting below error.
what would be the issue here ??

Error-[SVA-INVTYPE] Use of an invalid object
…/TESTBENCH/em_ahb5_assertions.sv, 354
“em_ahb5_assertions.region0_nonsec_check_mpu16”
The use of an object of type ‘assertion’ is not allowed in an assertion.

2

In reply to abhijain:

region0_nonsec_check_mpu16 : assert property(@(posedge clk)
disable iff(`AHB_LITE.ahb_htrans===2'b0 || disable_assertion==1 )
(haddr_in_r0 ) |-> ((mpu_region_s_r0 | set_ext_flag) !=`AHB_LITE.ahb_hnonsec)) else $fatal("\nERROR: set for MPU16 HIT_Region0 ");
// region0_nonsec_check_mpu16  is a label

You cannot do: cover property (region0_nonsec_check_mpu16);
Are you covering a label? You need to cover a property. Thus, the following is legal

 
property region0_nonsec_check_mpu16;
(@(posedge clk) disable iff(`AHB_LITE.ahb_htrans===2'b0 || disable_assertion==1 )
  (haddr_in_r0 ) |-> ((mpu_region_s_r0 | set_ext_flag) !=`AHB_LITE.ahb_hnonsec)) else
   $fatal("\nERROR: set for MPU16 HIT_Region0 ");
endproperty 
ap_region0_nonsec_check_mpu16: assert property(region0_nonsec_check_mpu16); 
cp_region0_nonsec_check_mpu16: cover property(region0_nonsec_check_mpu16);

\Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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3

In reply to ben@SystemVerilog.us:

thanks ben it worked the implementation was wrong