Correct property to count an event until another event happens

SystemVerilog
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7

In reply to salinerojj:
You are correct that the go-to repetition operator only accepts boolean values.
But I don’t see a sequence with the goto in the code.
BTW, the 2nd implication is not needed and not recommended.
Since the until is a property operator, I changed the code to intersect
see Reflections on Users’ Experiences with SVA - Part II


module m;
  bit event_1, event_2;   
  bit clk, enable;
  int counter_reference=10;
  property TEST;
    int count=0;
    @(posedge clk) enable |-> 
    ((event_1,count++)[->0:$] intersect event_2[->1]) ##0 
      count == counter_reference;   
  endproperty
  ap_TEST: assert property(TEST); 
endmodule