Correct property to count an event until another event happens

SystemVerilog
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4

In reply to Shubhabrata:

  1. You don’t need the first_match here
  2. Immediate assertion can be inserted anywhere, in an always, always_comb, always_ff, task, function, or in a block (e.g. module m; bit a, b; assert(a && b); endmodule)
    Ben