Correct property to count an event until another event happens

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Well, nicely explained. I got a few observations from this thread. I hope these are right.

  1. In the questions event_1, event_2 are not signals . They are triggering controllers. So
    the assertion wouldn’t be that simple and we cannot use repetition operators.

  2. To solve such questions, we have to implement functions and implicitly count them. And
    within the function, we can make an assertion one more time. Maybe there is a concept
    called a nested assertion.

  3. Now what if that event_1 and event_2 were signals? In that case, we could use the
    following way.


  module m;
  bit event_1, event_2;
  bit clk, enable;
  int counter_reference=10;
  property TEST;
    int count=0;
    @(posedge clk) enable |-> 
    first_match((event_1,count++)[->0:$]) until event_2 |-> count == counter_reference;  // 
    line 8
  endproperty
  ap_TEST: assert property(TEST); 
endmodule