In reply to salinerojj:
A very long long time ago when I was learning VHDL i used to ask a lot of questions.
Finally, a colleague gave me a good advice:
“Try a test code with the simulator; chances are that the simulator knows about the syntax much better than you”.
With this advice I did this because your code did not look right.
module m;
event event_1, event_2;
bit clk, enable;
int counter_reference=10;
property TEST(counter_reference);
int count;
@(posedge clk) enable |->
(event_1[=0:$],count=count+1) until event_2 ##0 count == counter_reference; // line 8
endproperty
ap_TEST: assert property(TEST(reference));
endmodule
Compiling module m
** Error: testbench.sv(8): (vlog-2110) Illegal reference to event "event_1".
** Error: testbench.sv(8): Illegal event value in SVA expression.
** Error: testbench.sv(8): Match items can not be attached to a sequence which admits empty match.
** Error: testbench.sv(8): (vlog-2110) Illegal reference to event "event_2".
** Error: testbench.sv(8): Illegal event value in SVA expression.
** Error: testbench.sv(8): Local variable count referenced in expression before getting initialized.
** Error (suppressible): testbench.sv(10): (vlog-1957) The sva directive is not sensitive to a clock. Unclocked directives are not supported.
** Error: testbench.sv(8): Local variable count referenced in expression before getting initialized.
Try something the following
module m;
event event_1, event_2;
bit clk, enable, a1, a2;
int reference=10;
task automatic count_events(int c);
bit done;
int count;
fork
while(done==0) @(event_1) count++;
while(done==0) @(event_2) done=1;
join
a_test: assert(count == c);
endtask
ap_test: assert property(@(posedge clk) enable |->
(1, count_events(reference)));
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
2) Free books:
* Component Design by Example https://rb.gy/9tcbhl
* Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
* A Pragmatic Approach to VMM Adoption
http://SystemVerilog.us/vf/VMM/VMM_pdf_release070506.zip
http://SystemVerilog.us/vf/VMM/VMM_code_release_071806.tar
3) Papers:
Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
Reflections on Users’ Experiences with SVA, part 1
https://verificationacademy.com/verification-horizons/march-2022-volume-18-issue-1/reflections-on-users-experiences-with-systemverilog-assertions-sva
Reflections on Users’ Experiences with SVA, part 2
https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-experiences-with-sva-part-2
SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/