Constraints

SystemVerilog
, ,
1

Hi,

I was trying to implement a constraint, where I have three rand variables or registers.

If I write a constraint like ‘a-b-c>0’, it gives ‘b’ and ‘c’ values as more than a. If I write the constraint as a>b+c, it works fine.
Is ‘a-b-c>0’ not the correct way to write it?

class a;
  
  rand bit [15:0]a;
  rand bit [15:0]b;
  rand bit [15:0]c;
  
  constraint c1{
    a - b - c > 0;
  }
endclass

module top;
  a a1;
  
  initial begin
    a1 = new();
  
    repeat(10) begin
      a1.randomize();  
      $display("a=%d, b=%d, c=%d", a1.a, a1.b, a1.c);
    end
  end
  
endmodule

Link for the code: Constraints_01 - EDA Playground

2

In reply to Akhil Mehta:
Your problem is a,b, and c are unsigned. Any non-zero result will be greater than 0. I think you want

    signed'(a - b - c) > 0;
3

In reply to dave_59:

Even with signed’(a-b-c)>0, I get results as:

a=31441, b=40149, c=35912
a=35754, b=62618, c=12990
a= 688, b= 9979, c=33886
a=14944, b=50266, c= 2779
a=34788, b=60539, c=17031
a=24745, b=49591, c=25592
a=30526, b=51056, c=35862

How are these cases valid? ‘a’ needs to be bigger than both b and c right?
Does compound expressions not work for SV constraints?

4

In reply to Akhil Mehta:

Sorry, didn’t notice that a,b, and c were 16 bits. You can do

signed'( 32'( a-b-c ) ) > 0; // or
int'( a-b-c ) > 0;
5

In reply to dave_59:

Thank you Dave, understood :)