In reply to Liiiiiz:
The result of the expression
item inside {[97:122]} is true 1’b1 or false 1’b0, both 1-bit. The sum() of those expressions will also be a 1-bit result. You just need to cast that expression to a large enough width so the sum of 10 possible 1’b1 values does not overflow. Cast to 4-bits or int would work as well. I think Alokpati used 7 because that was the element size of pw array, but that size is no longer relevant.
Only 10 numbers can be chosen because that is the size of the array, and the sum of all the sum constraints is exactly 10. At most one value between 40-46 can be chosen because there is a constraint that only allows one value between 33-46.
You might want to read my DVCon paper: SystemVerilog constraints: Appreciating what you forgot in school to get better results