Constraints to generate random password in SV

SystemVerilog
2

In reply to Liiiiiz:


module top;
 
  class A;
    rand bit [6:0] pw[];
     
    constraint inside0_10 {
      pw.size() ==10;
    }
    constraint uniq { 
      foreach (pw[i]) {
        pw.sum() with (7'(item inside {[97:122]}))==1; //a-z
        pw.sum() with (7'(item inside {[65:90]}))==1;  //A-Z
        pw.sum() with (7'(item inside {[33:46]}))==1;  //special char
        pw.sum() with (7'(item inside {[48:57]}))==7;  //0-9
      }    
    }
    
  endclass
 
  A a=new;
  initial begin
    repeat(10) begin
      assert(a.randomize());
      foreach(a.pw[i]) $write("%s ",a.pw[i]);
     $display("");
    end
  end
 
endmodule

Output:
v89F7’5817
24348S2(w0
,5540bY806
8L98s018&5
86E2463c%1
6x9M2.7854
8710Ka2#20
$76598a4Q1
9&7z5812Q6
84080F8,w6

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