Hi, I would like to know the difference between the two lines in the constraint statement below: class array ; parameter size = 10; parameter int UNIQ = 3; rand bit [5:0] array [size]; rand bit [5:0] rand_element; constraint AB { array.sum () with (int'(item == rand_element)) == UNIQ; // …

Hi, as Dave mentioned the expression will give a 1 bit value, which then needs to cast to int or larger width for the sum constraint to work.

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SystemVerilog, systemverilog-constraint

dave_59 April 11, 2024, 3:58am 2

Constraints to generate random password in SV SystemVerilog

In reply to Liiiiiz: The result of the expression item inside {[97:122]} is true 1’b1 or false 1’b0, both 1-bit. The sum() of those expressions will also be a 1-bit result. You just need to cast that expression to a large enough width so the sum of 10 possible 1’b1 values does not overflow. Cast to 4-bits or int would work as well. I think Alokpati used 7 because that was the element size of pw array, but that size is no longer relevant. Only 10 numbers can be chosen because that is the size…

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